Ultra Low Noise CMOS Image Sensors

The continuous improvements of CMOS image sensors (CIS) in terms of quantum efficiency, speed, resolution, etc. brought this low-cost devices into high-performance applications replacing progressively the charge coupled devices (CCDs). Photoelectron counting capability is the next step for CIS for ultimate low light performance and new imaging paradigms. With Recent improvements of CIS sensitivity, the sub-electron read noise limit has been reached. But this low noise level is still a bottleneck and further reduction towards deep sub-electron noise is required. A review of CMOS image sensors based on pinned photodiodes (PPD) is presented. Starting with a historical background, a summary of the PDDs physics is reviewed. The in-pixel readout circuit topologies exploiting the PPD are discussed fundamentally and the overall architecture of classical low noise CISs is presented. The physical mechanisms behind the random fluctuations affecting the signal at different levels of conventional CIS readout chains are reviewed and clarified. These include the photon shot noise, the dark current shot noise, the charge transfer nonidentities and the electronic circuits noise. Practical examples frommeasurements illustrating the different noise sources are presented. This thesis dedicates a particular focus to the readout circuit 1/ f and thermal noise given that these noises preclude the ultimate limit of photoelectron counting in conventional CIS. A detailed analytical calculation of 1/ f and thermal noise in readout chains based on the two possible in-pixel configurations is presented, namely the in-pixel source follower and common source topologies. The detailed analysis reveals process and design level noise reduction techniques. These are studied analytically and based on simulation results. Among the noise reduction techniques suggested by the analytical noise calculation, the increase of the oxide capacitance by using a thin oxide in-pixel amplifying transistor, for low 1/ f noise, is revealed for the first time. A readout chain design based on a thin oxide PMOS source follower is presented. The in-pixel source follower is optimally sized thanks to the analytical expression of the input referred 1/ f noise mentioned above. In order to validate the low noise performance of the newly proposed design. A test chip has been designed and fabricated in a 180 nmCIS process. It embeds small arrays of the proposed new pixels together with state-of-the-art 4T pixels based on buried channel source followers optimized at process level for low 1/ f noise. The new pixels feature a pitch of 7.5 μm and a fill factor of 66%. A mean input-referred noise of 0.4 e−rms is reported, for the first time, with a pixel designed in a iii